Careers

Nanochip solutions is a pioneer in providing technical solutions to customers working on Cutting edge technology. The engineering teams are managed by professionals who have worked in The USA for many years. We are looking for bright engineers aspiring to make it big in the VLSI and Embedded domain.

Apart from a good pay package we believe in constant upgradation of your technical skills and invest heavily in training and Skill enhancement programs for our employees.

We are currently looking to fill the following Entry & Senior Positions:

Entry Level ( 0 - 1 years )

Job Designation : Design Engineer

  • RTL Design Engineer – 0 to 1 yrs
  • ASIC Verification Engineer – 0 to 1 yrs
  • Synthesis & Timing Closure Engineer – 0 to 1 yrs
  • Physical Design Engineer – 0 to 1 yrs
  • Analog / Full custom Layout Engineer –0 to 1 yrs
  • Memory Layout Engineer – 0 to 1 yrs
  • Standard Cell Layout Engineer – 0 to 1 yrs

Senior Level ( 2 - 8 years)

Job Designation : Project Lead, Manager, Senior Manager

  • RTL Design Engineer – 2 to 8 yrs
  • ASIC Verification Engineer – 2 to 8 yrs
  • Synthesis & Timing Closure Engineer – 2 to 8 yrs
  • Physical Design Engineer – 2 to 8 yrs
  • Analog / Full custom Layout Engineer –2 to 8 yrs
  • Memory Layout Engineer – 2 to 8 yrs
  • Standard Cell Layout Engineer – 2 to 8 yrs
Eduction

BE/BTECH, ME/MTECH, MSc in EE with a min. percentage of 60%

Desired Knowledge

Good understanding of Digital design and timing concepts, ASIC Flow, Full custom flow. IC fabrication techniques, Designing using Verilog, Verilog for verification, Exposure to Synthesis and DFT. APR flow and Physical Verification and parasitic Extractions.

Desired skills

Candidates who have completed their PG/Advanced Diploma from reputed centers, engineers who have Done UG/PG projects in VLSI or Embedded Systems will be given a preference.

Other Skills

Excellent communication skills, team player, professional work ethics, knowledge of EDA tools from Cadence, Mentor Graphics And or Synopsys. Perl/Shell Programming. Working knowledge of Linux is highly desirable. Such experience from reputed finishing Schools is recognized.

Hot Openings

  • RTL Design Engineer – 0 to 8 yrs View more ..
  • ASIC Verification Engineer – 0 to 8 yrs View more ..
  • Synthesis & Timing Closure Engineer – 0 to 8 yrs View more ..
  • Physical Design Engineer – 0 to 8 yrs View more ..
  • Analog / Full custom Layout Engineer –0 to 8 yrs
  • Memory Layout Engineer – 0 to 8 yrs
  • Standard Cell Layout Engineer – 0 to 8 yrs
Click here for Hot Openings